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The following table provides R1 and R2 values for six high-speed logic families commonly used in optical data communications systems. Note that the
OP4012B can be used with logic families that run from a negative power supply voltage by simply using a negative V LOAD voltage.
Load Type
10K 3.3 V PECL
100K 3.3 V PECL
10K 5 V PECL
100K 5 V PECL
10K -5 V NECL
100K -5 V NECL
V DC
1.95
1.88
3.65
3.58
-1.30
-1.42
R1
120
120
180
180
240
240
R2
91
91
68
68
62
62
V LOAD
3.3 V
3.3 V
5.0 V
5.0 V
-5.0 V
-5.0 V
OP4012B Enable/Disable
Pin 3 on the OP4012B is the enable/disable control pin for the clock outputs. When Pin 3 is grounded, full output power is available from the clock. When
Pin 3 is pulled to Vcc, the power on the clock outputs is decreased at least 25 dB.
PLL for Generating a High Stability 644.53125 MHz Clock
External
Reference
Phase
Detector
+Vcc
Internal
Loop Filter
Tune
OP4012B
Q
Q
Reference
(holdover)
÷ N
Example OP4012B Phase-Locked Loop Application
One of the most important applications for the OP4012B is in a PLL circuit used to generate a very high quality 644.53125 MHz clock. The PLL combines
the long-term stability of a precision external or internal 20.1416 MHz reference clock with the very low jitter and phase noise of the OP4012B. A block
diagram of the PLL is shown in Figure 6. A sample of the OP4012B output is divided by 32 and is compared to 20.1416 MHz reference clock in the phase
detector. The loop filter at the output of the phase detector is set to a very low bandwidth (less than 50 Hz typical). This imparts the long-term stability of
the precision 20.1416 MHz reference to the OP4012B without degrading the OP4012B's low jitter and phase noise.
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?2008-2010 by RF Monolithics, Inc.
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OP4012B - 2/4/10
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